HyperTransport 1.x Specifications

HyperTransport 1.1 Specification (DirectPacket™)

HyperTransport DirectPacket™ Release 1.10 defines four major features to the HyperTransport 1.x technology specification:

• Native Packet Handling
• User packets move efficiently between devices without DMA loops
• Seamless mix of load-store and packet bus functionality
• Load-store operation with no added overhead
• Pier-to-Pier Routing
• Direct communication between HT devices
• Example: framer to security processor
• 16 Additional Virtual Channels
• Optimized for streaming
• Posted-Write only with dedicated flow control
• End-to-End flow control for highly channelized applications
• Example: channelized framer interface
• Robust Error Retry Protocol
• For high-reliability, mission-critical applications
• Future-proof - supporting faster electrical links

Such innovative DirectPacket™ capabilities make HyperTransport the most efficient means to stream packets with minimum overhead and the ideal technology for enhancing performance in high speed streaming data with SPI-4, XAUI, and other communications technologies. HyperTransport DirectPacket™ features bring communications-oriented, packet-handling capabilities to otherwise standard processor-centric computing systems.

HyperTransport 1.05 Specification

The HyperTransport 1.05 Specification adds four major features to the previous HyperTransport 1.03 release:

• HyperTransport Link Switch Function
• Enables connection of virtually unlimited numbers of HyperTransport devices
• Enhanced PCI-X 2.0 Inter-Working
• Simplifies connection to PCI-X 2.0 subsystems
• Supports error indications and device configuration messages up to 4K bytes
• Supports PCI-X 2.0 128-byte burst messaging
• Extended Transaction Concurrency
• Allows up to 128 outstanding requests
• Eliminates potential bottlenecks in networking applications
• Extended 64-bit Addressing
• Extended from 40-bit
• Supports larger address topologies required by large server and networking applications
• Backward compatible with earlier generation addressing schemes

HyperTransport 1.04 Specification

The HyperTransport 1.04 Specification introduces feature extensions, clarifications and errata fixes to the original HyperTransport 1.03 Release:

• Revision ID Capability
• For tagging functions as existing within an HT device
• PCI-X Ordering and Command Mapping
• Simplifies connection to PCI-X 2.0 subsystems
• Potential Deadlocks Prevention
• How to prevent – Documented in Appendix C

HyperTransport 1.03 Specification

HyperTransport 1.03 is the original HyperTransport™ I/O Link specification released by the HyperTransport Consortium in October 2001. HT 1.03 defines and describes the input/output link protocol and electrical interface for the HyperTransport interconnect technology. The document is divided into two main parts: Protocol and Electrical. The Protocol part includes information on HyperTransport technology signals, packets, commands, interrupts, configuration accesses, address map, error handling, clocking, and initialization. The Electrical part includes information on I/O power supply, AC and DC characteristics, transfer timing, and phase recovery timing.