HyperTransport 3.0 Specification

HyperTransport 3.0 is the latest release of the HyperTransport specification introduced in April 2006. The new HT 3.0 standard nearly doubles the clock speed and bandwidth of HT 2.0 while delivering a full slate of powerful scalability and power management features.

HyperTransport 2.0 Features Plus:

• 1.8 GHz, 2.0 GHz, 2.2 GHz, 2.4 GHz and 2.6 GHz Clock Rates
  • 41.6 GB/s Max Aggregate Bandwidth (32-bit)
  • 20.8 GB/s (166.4 Gb/s) Max Bandwidth per Unidirectional HT Link (32-bit)
  • 5.2 GT/s (2.6 GHz x 2 DDR) per Bit
• Link Splitting (Un-Ganging) – Optional
  • Each unidirectional HT link reconfigurable in real time and under software control from any given bit width – i.e. 32-bit, 16-bit, 8-bit, 4-bit - to two independent unidirectional links having half the bit width of the original link
  • Auto-Configuration
  • Asymmetry Support
    • Unidirectional HT links within each HT port can have different bit width
  • Powerful scalability feature - doubles the number of per-product HT ports
  • More HT ports particularly useful in Symmetric Multi-Processing (SMP) topologies
• Enhanced Power Management
  • HT link clock rate and bit width constantly and dynamically adjusted for best power consumption and given workload. Real-time decision-making and adjustments handled by HT control logic via link traffic load monitoring transparently to operating system and end-user applications
  • Rapid Pause-Change-Start
• DC Operating Mode Enhancements
  • Transmitter:
    • Enhanced Training Pattern Tolerates Multi-Bit Skew
    • Added Scrambling Enables Rx Phase Alignment
    • Retained DDR Clock
  • Receiver:
    • Enabled Use of Rx Equalization
    • Support for Multi-Bit Skew Through Clock-Based Rx Phase Alignment
• AC Operating Mode – Optional
  • Capacitive Coupling (vs. Direct Coupling of DC Mode)
  • 8B/10B Clock Recovery
  • Triples HT’s Max Link Length to 1m/3ft at Max Clock Rate
    • Cables, Backplanes, Chassis-to-Chassis Applications
  • Higher Latency than DC Mode
  • Enabled when Needed – Best of Both Worlds (DC and AC Mode)
• DC /AC Auto-Configuration
  • Coupling Capacitors Auto-Detect sets HT Link to AC mode
  • Same HT device configurable in DC Mode for short runs and AC mode for long runs
• Hot Plugging
  • HT devices added or removed without disrupting product/system operation
    • Defined Link Termination Methods
    • Transaction Termination Behaviors
    • Sync Flood Isolation
    • Link Training Times
  • Parameter Configuration Mechanisms
  • "Always-up" capability for backplane and mission-critical applications
• 100% Backward Compatibility
  • Runs in HT 1.x and 2.0 Mode when New Features Not Enabled
    • Boot-Up Auto-Configuration
  • HT Link Set to Highest HT Specification Revision Supported by all HT Link Devices

State-of-the-Art Technology - Investments Preservation

These new HyperTransport 3.0 features and capabilities dramatically reinforce HyperTransport's role as the most flexible, most scalable, highest performance and lowest latency processor-to-processor and processor-to-peripheral interconnect technology the market has to offer, vastly extending its overall application latitude and market opportunity. In addition, by preserving full backward compatibility with prior HyperTransport specifications, HyperTransport 2.0 continues to safeguard and maximize the industry’s legacy investments in the technology.

 HyperTransport Specification 3.0 Revision D with change bars
 HyperTransport Specification 3.0 Revision C with change bars
 HyperTransport Specification 3.0 Revision B with change bars
 HyperTransport Specification 3.0 Revision A
 HyperTransport 3.0 Specification First Release