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Altera Corporation

APEX II EP2A70  from 

Product Type: FPGA

Altera introduces the APEX" II device family: high performance, high-bandwidth programmable logic devices (PLDs) targeted towards emerging network communications applications and protocols. APEX II devices support protocols such as the UTOPIA IV, RapidIO", CSIX, and POS-PHY Level 4 protocols, making them the ideal solution for complex systems. The APEX II device family features 1-gigabits per second (Gbps) dedicated True-LVDS" circuitry, phaselocked loops (PLLs), embedded system blocks (ESBs), content-addressable memory (CAM), and enhanced all-layer-copper interconnects.

Product Features:

  • Advanced High-Performance LVDS
  • 36 1-Gbps True-LVDS input and 36 1-Gbps True-LVDS output channels
  • Up to 88 624-megabits per second (Mbps)
  • Flexible-LVDSTM input channels and 88 624-Mbps
  • Flexible-LVDS output channels
  • LVDS/LVPECL/PCML/HyperTransport" I/O support
  • Supported I/O Protocols
  • RapidIO
  • POS-PHY L4
  • Flexbus
  • PCI-X
  • UTOPIA IV
  • CSIX
  • LCS
  • Zero-bus turnaround (ZBT), double-data rate (DDR), and quad-data rate (QDR) memory interface support
  • Enhanced Architecture
  • 4 Kbits of memory per ESB
  • Dual-port+ RAM in ESBs with bidirectional read/write ports
  • Eight PLL output taps
  • Six high-speed registers per I/O element

The high-density Altera® APEX II device family offers advanced I/O features to support a total systemon- a-programmable-chip (SOPC) solution. APEX II FPGAs are based on a 0.15-/0.13-µm all-layer-copper interconnect technology to address the increasing performance and bandwidth requirements of communication applications. These devices offer versatility and flexibility for highperformance SOPC applications.

The APEX II device densities range from 16,640 logic elements (LEs) to 67,200 LEs. Based on state-of-the-art SRAM process technology, the APEX II device family supports a wide range of high-speed I/O standards such as LVDS, PCML, LVPECL, HyperTransport, HSTL, and SSTL, enabling high-speed I/O data transfers. With True-LVDS circuitry, APEX II devices can achieve data transfer rates of up to 1 Gbps per channel, and are fully 64-bit, 66-MHz PCI and PCI-X compliant. APEX II devices feature four general-purpose PLLs that can drive eight different global clock nets and/or circuit signals for comprehensive clock management and synthesis needs.

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Related HyperTransport-enabled products:
Other HyperTransport-enabled products from Altera Corporation

Product Type    

Product Detail

Reference Designs    
HTX-based 10 Gigabit Ethernet Board Reference Design

The HTX-based 10GE Board Reference Design from ALTERA Corporation is a fully validated and tested platform based on ALTERA's Stratix II FPGA core, featuring 2 x 10GE ports. The reference design is a turn-key, quick time-to-market 10GE Network Interface Card (NIC) development vehicle, downloadable free-of-charge from the HyperTransport Consortium web site, complete with board schematics, Gerber files and all other relevant board level documentation.

The reference design does not include any MegaCore logic functions, any design files provided in encrypted netlist or encrypted source code formats, nor any design files provided under Altera's OpenCore and OpenCore Plus programs, which are subject to other applicable license agreements for which interested parties must engage with ALTERA directly.

Click here to download the reference design

FPGA    
Stratix EP1S25

Stratix® devices contain powerful system-level features that offer design flexibility and high-performance system integration. As part of a general-purpose device family, Stratix devices offer a feature-rich, high-bandwidth system solution to take system-on-a-programmable-chip (SOPC) designs to new levels. Stratix II FPGAs are built for designers who need higher performance, higher density, and lower cost.

Product Features:

  • High-Performance Architecture
  • High Memory Bandwidth & High-Speed External Memory Interfaces
  • High-Performance Digital Signal Processing
  • High I/O Bandwidth & High-Speed Interfaces
  • System Clock Management
  • Automatic Cyclic Redundancy Code (CRC) Checking
  • On-Chip Hot-Socketing & Power-Sequencing Support
  • Remote System Upgrade Capabilities
  • Embedded Processor Cores
  • Low-Cost Volume Production Devices

Altera's high-density Stratix® FPGAs power complex designs to high levels of system integration. Introduced in 2002, Stratix devices are shipping in volume production, including commercial- and industrial-grade devices. Customers ready to ramp their system-on-a-programmable-chip (SOPC) designs in production have immediate access to production versions of the high-performance Stratix devices through Altera's distribution channels. Designers needing higher performance, higher density, and lower cost can take advantage of Stratix II FPGAs.

The rapid deployment of next-generation systems has been accompanied by a dramatic increase in demand for total FPGA bandwidth. Instead of being restricted to non-critical peripheral processes, as are many FPGAs, Stratix devices can be used at the heart of high-bandwidth systems to accelerate performance and enable new functionality.

The Stratix device family is based on a 1.5-V, 0.13-µm, all-layer-copper process technology and offers up to 79,040 logic elements (LEs), 7 Mbits of embedded memory, optimized digital signal processing (DSP) blocks, and high-performance I/O capabilities. Stratix devices are the ideal solution for complex, high-performance systems.

Stratix devices have a rich set of advanced features, including:

  • A high-performance architecture that accelerates block-based designs for maximum system performance
  • Abundant TriMatrix" memory resources for on-chip storage
  • High-bandwidth DSP blocks for signal processing-intensive applications
  • Proven differential I/O technology featuring the True-LVDS" circuitry, capable of 840-Mbps performance
  • Robust clock management and frequency synthesis for managing on- and off-chip timing to maximize system performance using full-featured, embedded phase-locked loops (PLLs)
  • Maximized signal quality and data transfer reliability with differential and series on-chip termination

The Stratix architecture has also been designed to maximize the performance benefits of the Nios® II family of embedded processors. The advanced architectural features of Stratix devices combined with the Nios II embedded processors improve the performance of the soft embedded processors to over 150 DMIPS, offering very high processing power for high-bandwidth systems.

When used in conjunction with an extensive intellectual property (IP) core portfolio and the easy-to-use Quartus® II development software, users can minimize time-to-market on high-bandwidth designs.

System designers who require a low-risk cost-reduction path for high-volume production can migrate their Stratix designs to fixed-function HardCopy Stratix" devices. HardCopy Stratix devices maintain the high-density, high-performance architecture of Stratix FPGAs and offer a low-cost, seamless migration path to high-volume, application-specific, mask-programmed devices. Though highly design-dependent, HardCopy Stratix devices can also offer an average of 50 percent higher performance and about 40 percent lower power consumption compared to Stratix FPGAs.

Find answers to common questions about Stratix devices on the Questions & Answers page. Also, see what customers are saying about the new Stratix device family.