University of Heidelberg (Germany)

The Altera HTX3 board reference design from the HT Center of Excellence (HTCE) provides an easy and efficient way to evaluate FPGA-based board-level subsystems directly connected to any AMD Opteron™ processor node via a slot connector compatible with a 16-bit wide HyperTransport HTX3™ Interface Specification. The HTX3 board employs a single Stratix IV FPGA with 228K logic elements, which provides ample silicon resources for implementing an HT3-Core and user-specific functionality platform. To support the high clock rates of the HT3 interface, serial transceiver (GTP) blocks are used for the HT links. With such links, the HTX3 Board is capable of providing bidirectional I/O bandwidth of up to 8 GB/s. The HTX3 Board integrates 256MB of DDR3 memory, USB2.0 interface and CX4 connectors.

Product Features

• HTX3 Connector with 16-Bit GTP-Based Bidirectional Interface

• 1x Altera Stratix IV FPGA with 228K Logic Elements

• 256 MB of DDR3 Memory

• 2x CX4 Connectors Connected to the FPGAs via High-Speed Serial Links (GTPs)

• 1x Ethernet Port (Marvell 88E1111)

• 1x USB2.0 Port (Cypress CY7C68013A)

• 3x Samtec QTH Connectors and 1x Samtec SEAF Connector for Additional Standard Interfaces

• 1x JTAG FPGA Programming Interface

• Only 12V and 3.3V Power Supply via the HTX3 Connector

An HTX-Extender board with test pins for logic state analyzer connection is available as option, allowing direct measurement of all HT signals.

The Altera HTX3 Board can also be used as a stand-alone FPGA design testing platform.

• Altera HTX3 Board Datasheet

• Altera HTX3 Board Reference Design Download

The HTX3 Board is a development of the University of Heidelberg, ZITI, Computer Architecture Group.

More Information and Contacts

For more information on the HTX3 Board, please contact Prof. Ulrich Bruening - ulrich.bruening@ziti.uni-heidelberg.de, +49-(0)621-1812723, Fax +49-(0)621-1812713.

UoH's HT-Core IP is a low latency, queue-based application interface, non-coherent HyperTransport cave core - i.e. endpoint device in an HT interconnect daisy chain - for an efficient implementation of user-specific, HyperTransport-based IC devices. With the use of programmable logic devices (FPGAs, the HT-Core enables quick evaluation and design of HyperTransport control functions directly linked to the main system CPU(s) via standard HyperTransport links or via HTX slot connectors. The HT-Core can be used in conjunction with UoM's HTX Board Universal Reference Design and mapped into the board's high performance FPGA (Xilinx Virtex-4 FX60). The HT-Core is available at no cost to the industry.

Product Features:

• Coherent HT Cave

• 4 x queues - Posted, Non-Posted, Response, Probe - for each HT link direction

• 400 MHz HT link clock

• 200 MHz internal clock

• Up to 3.2 GB/sec bidirectional bandwidth at 400 MHz HT clock

• 2-, 4-, 8-, or 16-bit bidirectional HT interface designed for Xilinx I/O cells

• Internal data path 4x the HT link width (32/64 bits)

• Xilinx Virtex-4 FPGA product series programmable core

• Compliant with AMD's Coherent HT I/O Link Specification

• Very low latency architecture

• Fully synchronous design

• Efficient pipeline structure

• Use of minimal hardware resources

• Suitable for connecting a coherent, cache-based device or coherent cache-based processor to any AMD Opteron CPU

• Test and debug configuration files for Cadence Simvision

• Synthesizable Verilog HDL code

Deliverables:

• Verilog source code verified with a Xilinx Virtex-4 FX60 series FPGA on the HTX-Board installed on an Iwill/Flextronics DK8-HTX server motherboard equipped with Linux-BIOS

• Constraint file in Xilinx .ucf file format with pinout information

Licensing:

The HT-Core is available under an open source license to any interested party. The acquiring party is obligated to secure a HyperTransport technology license if and by the time any of the party's products based on the HT-Core is openly promoted or sold. A royalty-free HyperTransport technology license can be obtained by simply becoming a member of the HyperTransport Technology Consortium. Information on HyperTransport Consortium membership classes, benefits, fees and application guidelines can be found here.

Downloads and Contacts:

The above HT-Core deliverables can be freely downloaded from CoEHT's web site through a simple registration process. For more information on the HT-Core, application examples and registration, please visit UoH's HyperTransport Center of Excellence web site (link below), or contact Prof. Ulrich Bruening - ulrich.bruening@ziti.uni-heidelberg.de, +49-(0)621-1812723, Fax +49-(0)621-1812713.

UoH's HTX-Extender - Model A suits a variety of test and measurement needs by enabling easy access to all signals of a standard HTX expansion connector. Coupled with a logic state analyser, the HTX-Extender - Model A is best suited for general purpose HTX signal probing with flying test leads. The extender plugs between the Device-Under-Test (DUT) and the HTX connector of the systemboard or riser card.

Product Features:

• Compatible with any standard HTX connector and HTX-based products

• Enables testing of all 16-bit data, clock and control HT signals in each unidirectional HyperTransport link

• 16-bit LVDS bidirectional interface

• Allows current measurement for all HTX voltages

• Accessibility to all differential signals for 8-bit mode

• Impedance-controlled design

• Dimensions: 160mm x 55mm x 23 mm (approx.)

The HTX-Etender - Model A allows easy testing of the following signals and voltages:

Differential Signals

• CADIN_H/L[15:0]

• CADOUT_H/L[15:0]

• CLKIN_H/L[1:0]

• CLKOUT_H/L[1:0]

• CTLIN_H/L

• CTLOUT_H/

• REFCLK_H/L

Single-Ended Signals

• REFCLK66

• PWROK

• RESET#

• JTAG_TMS, _TDO, _TDI, _TCLK and _RST#

• LDTSTOP#

• SM_CLK and SM_DAT

Supply Voltages

• 12 Volts

• 3.3 Volts

• 3.3 Volts (aux)

• 1.2 Volts (VLDT)

Differential signals are accessible over a 1.27mm stripline. Single-ended signals over a stripline with a pitch of 2.54mm. No additional vias are introduced for the differential signals. Test points for signals located on the B-side of the HTX connector are on the top side of the extender, while test points for signals located on the A-side of the HTX connector are on the bottom side of the extender.

Current measurement for each supply voltage of the HTX connector is done by measuring the voltage drop across a 0.1 Ohm resistor accessible via a 2.54mm stripline.

HTX Extender - Model A Datasheet

More Information and Contacts:

For more information on the HTX Extender - Model A, please contact Prof. Ulrich Bruening - ulrich.bruening@ziti.uni-heidelberg.de, +49-(0)621-1812723, Fax +49-(0)621-1812713.

UoH's mezzanine board enables easy design of customer-specific interface modules (e.g. debug modules).

Product Features:

• Plugs into widely used Samtec connector (2 available on the HTX-Board)

• 10-bit wide LVDS

• Single-ending possible

• 2 x CAT7 connectors

• 1.8 Volts and 3.3 Volts

More Information and Contacts:

For more information on the HTX Extender - Model B, please contact Prof. Ulrich Bruening - ulrich.bruening@ziti.uni-heidelberg.de, +49-(0)621-1812723, Fax +49-(0)621-1812713.

The Xilinx HTX Board Reference Design is the answer to rapid product prototyping, validation enablement and efficient time-to-market for user-specific, high-performance compute acceleration, server clustering, security processing, packet processing, media acceleration and communication subsystems based on the HyperTransport Consortium's HTX slot connector standard. The HTX-Board's core is a powerful and programmable Xilinx Virtex-4 FPGA device. With its 16-bit wide bidirectional HTX interface, it can directly connect to any AMD Opteron-class processor node and be plugged into any HTX-equipped motherboard or system product from a wide range of manufacturers. The HTX Board features 3.2 GByte/s of bandwidth and lowest transaction latency. The HTX Board design supports a number of interface standards. Additional interface standards can be accommodated via two mezzanine connectors.

Product Features:

• HTX Connector with 16-bit LVDS bidirectional interface

• Xilinx Virtex-4 FX100 FPGA

• 125 MHz low jitter clock oscillator

• 256 MB of DDR2 DRAM 32-bit interface to FPGA

• 512 Mb of user flash memory, 16-bit interface to FPGA

• JTAG and USB1.1 interface for FX100 PROM programming

• Programming infrastructure

• USB interface for FPGA-to-PC communication

• 6 x high speed serial links with Small Form Factor Pluggable (SFP) transceivers

• Gigabit Ethernet transceiver with RJ45 connector

• SATA connector

• Power fed through HTX connector - no external power supply required

• 6 to 24W power consumption

An HTX-Extender board with test pins for logic state analyzer connection is available as option, allowing direct measurement of all HT signals. The HTX-Board can also be used as a stand-alone FPGA design test bed. A complete PowerPC computer system can be programmed into the FPGA.

• HTX-Board Overview

• HTX-Board Datasheet

The HTX Board is a development of the University of Heidelberg (UoH). It has been partly funded by the European Union in the context of the FutureDAQ Project under contract number RII3-CT-2004-506078.

More Information and Contacts

For more information on the HTX Board, please contact Prof. Ulrich Bruening - ulrich.bruening@ziti.uni-heidelberg.de, +49-(0)621-1812723, Fax +49-(0)621-1812713.

The Universal HTX3 Board Reference Design provides an easy and efficient way to evaluate user specific devices connected to the HyperTransport 3 connector standardized in accordance with the HyperTransport HTX3™ Connector Specification. The HTX3 Board with its 16-bit wide high speed serial transceiver-based HTX3 interface can be directly connected to any AMD Opteron™ processor node through the HTX3 connector interface. The HTX3 board employs 3x Virtex 5 FPGAs to provide enough silicon resources for implementing an HT3-Core and user-specific functionality platform. To support the high clock rates of the HT3 interface, serial transceiver (GTP) blocks are used for the HT links. With such links, the HTX3 Board is capable of providing bidirectional I/O bandwidth of up to 8 GB/s. The HTX3 Board integrates USB2.0 interface, CX4 connectors and SODIMM socket for memory expansion.

Product Features

• HTX3 Connector with 16-Bit GTP-Based Bidirectional Interface

• 1x FPGA Virtex-5 LX110T (larger ones on request)

• 2x FPGA Virtex-5 LX50T (larger ones on request)

• 1x SODIMM socket for up to 2 GB of RAM.

• 256 Mb of Non-Volatile User Flash RAM with 16-Bit Interface to the FPGA

• 2x CX4 Connectors Connected to the FPGAs via High-Speed Serial Links (GTPs)

• 1x USB2.0 Port

• Only 12V and 3.3V Power Supply via the HTX3 Connector

• 6 to 40W of Power Consumption

The FPGA can be configured via JTAG, USB or by flash memory.

An HTX-Extender board with test pins for logic state analyzer connection is available as option, allowing direct measurement of all HT signals.

The HTX3 Board can also be used as a stand-alone FPGA design testing platform. A complete PowerPC computer system can be programmed into the FPGA.

• HTX3 Board Datasheet

The HTX3 Board is a development of the University of Heidelberg, ZITI, Computer Architecture Group.

More Information and Contacts

For more information on the HTX3 Board, please contact Prof. Ulrich Bruening - ulrich.bruening@ziti.uni-heidelberg.de, +49-(0)621-1812723, Fax +49-(0)621-1812713.

UoH's cHT-Core IP is a low latency, queue-based application interface, coherent HyperTransport cave core - i.e. endpoint device in an HT interconnect daisy chain - for an efficient implementation of user-specific, coherent HyperTransport-based IC devices. With the use of programmable logic devices (FPGAs, the cHT-Core enables quick evaluation and design of HyperTransport control functions directly linked to the main system CPU(s) via standard HyperTransport links or via HTX slot connectors. The cHT-Core can be used in conjunction with UoM's HTX Board Universal Reference Design and mapped into the board's high performance FPGA (Xilinx Virtex-4 FX60). The cHT-Core allows users to build HyperTransport devices with coherent caches, or to enable custom processors to interface with coherent HyperTransport links.

Product Features:

• Coherent HT Cave

• 4 x queues - Posted, Non-Posted, Response, Probe - for each HT link direction

• 400 MHz HT link clock

• 200 MHz internal clock

• Up to 3.2 GB/sec bidirectional bandwidth at 400 MHz HT clock

• 2-, 4-, 8-, or 16-bit bidirectional HT interface designed for Xilinx I/O cells

• Internal data path 4x the HT link width (32/64 bits)

• Xilinx Virtex-4 FPGA product series programmable core

• Compliant with AMD's Coherent HT I/O Link Specification

• Very low latency architecture

• Fully synchronous design

• Efficient pipeline structure

• Use of minimal hardware resources

• Suitable for connecting a coherent, cache-based device or coherent cache-based processor to any AMD Opteron CPU

• Test and debug configuration files for Cadence Simvision

• Synthesizable Verilog HDL code

Deliverables:

• Verilog source code verified with a Xilinx Virtex-4 FX60 series FPGA on the HTX-Board installed on an Iwill/Flextronics DK8-HTX server motherboard equipped with Linux-BIOS

• Constraint file in Xilinx .ucf file format with pinout information

Licensing:

The cHT-Core is available under the Coherent HyperTransport License from AMD. Please contact AMD for further details about licensing and delivery of the core (for AMD contacts, please email the HyperTransport Consortium at info@hypertransport.org). The acquiring party will be also obligated to secure a HyperTransport technology license if and by the time any of the party's products based on the cHT-Core is openly promoted or sold. A royalty-free HyperTransport technology license can be obtained by simply becoming a member of the HyperTransport Technology Consortium. Information on HyperTransport Consortium membership classes, benefits, fees and application guidelines can be found here.

More Information and Contacts:

For more information on the cHT-Core, please visit UoH's HyperTransport Center of Excellence web site (link below), or contact Prof. Ulrich Bruening - ulrich.bruening@ziti.uni-heidelberg.de, +49-(0)621-1812723, Fax +49-(0)621-1812713.