Lattice Semiconductors

LatticeSC/M FPGA Families Deliver Fast HyperTransport and Memory Interfaces

The LatticeSC/M (System Chip/MACO) family of FPGAs support HyperTransport technology at rates up to 1600Mbps, QDRII+ rates up to 750Mbps, RLDRAM II rates of 800Mbps and DDR2 interface speeds of 667Mbps. HyperTransport technology and the memory interfaces are implemented using the LatticeSC/M families' innovative PURESPEED I/O technology.

LatticeSC/M FPGAs combine high-performance FPGA fabric, 3.8Gbps SERDES and PCS, 2Gbps Parallel I/Os, low-power 1V Vcc option, large embedded RAM, and embedded ASIC blocks to provide the highest performing FPGA in the industry.

Fastest HyperTransport Interface in FPGA Industry

The LatticeSC/M's PURESPEED I/O technology supports HyperTransport interfaces operating as fast as 1600Mbps - twice the performance of competing FPGA platforms. This significant improvement in HyperTransport interface speed is extremely attractive to users who rely on FPGAs in HyperTransport-based, application-specific co-processing subsystems.

Memory Controllers Optimized With MACO

Lattice's unique embedd MACO (Masked Array for Cost Optimization) design technology delivers state-oif-the-art memory speeds. The use of embedded technology reduces the FPGA resources - both logic gates and power - needed to implement these controllers. In addition, Lattice's pre-engineered design functions enable users to reduce design cycles and thereby quicken the end-system time-to-market. MACO technology is available on the LatticeSCM family of devices (not included with the LatticeSC family).

HyperTransport Center of Excellence's HT-Core ported to LatticeSC FPGA family

The HyperTransport Center of Excellence (HTCE) at the University of Mannheim has ported its HT-Core into the LatticeSC/M FPGA products. Users are therefore able to use LatticeSC/M FPGA products as one of the target devices for HTCE's HT-Core. HTCE's core is a non-coherent HyperTransport Cave device (endpoint). The HT-Core is available under an open source license to any third party. For commercial use of the HT-Core, a royalty-free technology license can be obtained by simply joining the HyperTransport Technology Consortium.

LatticeSC/M HTX Evaluation Board and Reference Design

Lattice has developed an HyperTransport HTX-based evaluation board that supports user demos of the HT-Core in a LatticeSC/M device.

Product Overview

The LatticeSC FPGAs feature PURESPEED I/O technology, combining powerful buffers with dedicated I/O Logic to provide seamless and robust parallel source synchronous I/O solutions. The resulting solution packs a powerful punch providing support for an industry-best 2Gbps throughput per differential I/O pair. PURESPEED I/O technology consists of:

• Highly flexible, built-in shift register and DDR/SDR Mux/Demux logic

• A highly granular (144 taps) programmable Input Delay (INDEL) block with Adaptive Input Logic (AIL) to dynamically align source synchronous signals on a per-bit basis for industry leading performance

• Dedicated Clock Divider circuitry for by-2 and by-4 clock division

• Support for the following system level standards:

• Powerful PURESPEED I/O buffers supporting:

• Programmable On Die Termination

PURESPEED I/O Buffer

Programmable I/O buffers are arranged around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users to implement the wide variety of standards that are found in todays systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. The availability of programmable on-die termination for both input and output use, further enhances the utility of these buffers.

Supported I/O Standards

The LatticeSC sysIO buffer supports both single-ended and differential standards.

Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, PCI clamp or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP2X33. Differential standards supported include LVDS, RSDS, BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. The table below shows the I/O standards (together with their supply and reference voltages) supported by the LatticeSC devices.

Supported Source Synchronous Interfaces

The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify the implementation of Source Synchronous interfaces. The table below lists Source Synchronous and DDR/QDR standards supported in the LatticeSC.