HyperTransport Material from Consortium Members

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2009
	In-Server Content-Aware Routing Network Interface Card Along with incremental performance capability, multicore system architectures lead to increased challenges in terms of efficient data routing – i.e. the ability to decide to which specific processor core data packets received from the network belong and should be directed to for processing. This white paper looks into the increased efficiency and performance optimization of an innovative, HT-based technology called “Content Aware Routing” which combines real-time analysis and classification of data packet traffic with ability of directing it to the specific processor cores within the same server system or to other servers within the server cluster as appropriate.
2008
	In-Socket Accelerators – When to Use Them This paper analyzes the opportunities and values that in-socket, FPGA-based accelerators bring to the HPC market. It also discusses their typical applications and the way they can be system-deployed.
	Software to Hardware Parallelization The white paper discusses important software parallelization steps required to perform efficient algorithms acceleration on multi-core platforms.
	Reconfigurable Computing for Acceleration in HPC This paper explores the technical and business merits of FPGA-based, reconfigurable accelerators that leverage the direct connect and low latency capabilities of HyperTransport technology.
2007
	Advanced Glass Reinforcement Technology for Improved Signal Integrity The white paper reviews some innovative PCB laminate technology that answers the signal integrity challenges of modern multi-GHz designs.
2006
	XtremeData - FPGA Acceleration in HPC: A Case Study in Financial Analytics - November 2006 The white paper discusses recent trends in High Performance Computing (HPC) and the opportunity for the HPC industry to leverage the compute power and flexibility of FPGA co-processing, especially in applications demanding fast time to results and the need for frequent updates to the acceleration algorithms. Financial analytics is the application case study.
	AMD - Building Next-Generation Telecom Equipment Based on the AMD64 Processor Family This paper explains that it is now possible to design dense and high-performance computing and I/O blades for telecom equipment at a price/performance point that is ideal for standardized platforms such as Advanced TCA, MicroTCA, ATCA/AMC, CompactPCI and VME. Examples are given showing how the AMD Opteron processor’s features and benefits can help solve the challenges of building next-generation telecom equipment. The paper will conclude with an overview of the extensive hardware, software and development support for the AMD64 ecosystem.
2005
	PathScale - Beyond Hero Numbers - Factors Affecting Interconnect Performance - June 2005 The paper analyzes the key role of interconnect performance in the realm of ever-larger system clusters and multi-processor applications.
	Newisys - HORUS - Large Scale SMP Using Opteron™ Processors - April 2005 The paper describes the implementation of a coherent HyperTransport-based ASIC called HORUS. The HORUS chip enables Newisys' large scale, partitionable, fault tolerant, Symmetric Multi-Processor (SMP) systems.
	AMD Opteron Processors - A Better High-End Embedded Solution - March 2005 AMD discusses the adantages offered by the Opteron processor as the core of high-performance embedded designs. The paper also discusses how Opteron's support for Direct Connect Architecture and HyperTransport / HTX connectivity further enhance Opteron's appeal as a leading embedded system platform and give the industry new ways to attain maximum performance while keeping system integration and ease of design at their highest levels.
2003
	Agilent Technologies - Testing HyperTransport™ Backgrounder - Spring 2003 Design guide for testing HyperTransport devices - by Agilent Technologies.
	Xilinx - The HyperTransport 'Lite' Interface for Virtex®-II FPGAs Application Note - January 2003 This application note discusses the "Lite" interface for use with Xilinx Virtex II FPGAs.
2002
	Xilinx - HyperTransport™ High Speed I/O with Virtex®-II - Summer 2001 The article discusses the implementation of HyperTransport™ interfaces with Virtex®-II FPGAs.